Intel Pentium MMX
Configuration
Intel Pentium MMX 233 MHz (250nm) + ALi ID1531 + SDRAM-66 CAS:3
Cache
L1 Data cache = 16 KB. 32 B/line. 4-Way
L1 Instruction cache = 16 KB. 32 B/line, 4-WAY.
L2 cache size = 1 MB. direct-mapped? 32-byte line size?
4 KB pages mode
TLB size = 64 items.
Size
Latency
Description
16 K
2
TLB + L1
256 K
2 + 80 ns
+ 80 ns (L1-Cache miss, L2 hit)
1 M
2 + 220 ns
+ 140 ns (TLB miss)
...
2 + 390 ns
+ 170 ns (L2 miss, RAM access)
MISC
Branch misprediction penalty = 4 cycles.
4-bytes range cross penalty = 3 cycles.
L2 Read B/W (32 Bytes stride) = 15 (64 ns) cycles per cache line (466 MB/s)
L2/RAM Write B/W (8 Bytes stride) = 13-15 cycles per write (130 MB/s)
RAM Read B/W (32 Bytes stride) = 215 MB/s
Links
Intel Pentium MMX at Wikipedia