L1 Data cache = 32 KB. 32 B/line.
TLB size = 32 items.
| Size | Latency | Description |
|---|---|---|
| 32 K | 3 | TLB + L1 |
| 128 K | 3 + 300 ns | + 300 ns (RAM) |
| ... | 3 + 960 ns | + 660 ns (TLB miss, + 2 * RAM accesses) |
RAM Read B/W (4 Bytes stride) = 60 MB/s
RAM Read B/W (32 Bytes stride) = 107 MB/s
RAM Write B/W (4-16 Bytes stride) = 260 MB/s
Branch misprediction penalty = 4 cycles.