ARM11

Hisilicon SD5113 (ARM11) 530 MHz, 16-bit DDR2-667, Huawei EchoLife HG8245 GPON Terminal.

4 KB pages mode

Size Latency Description
16 K 4 TLB + L1
40 K 4 + 180 ns + 180 ns (RAM)
256 K 12 + 180 ns + 8 (L1 TLB Miss)
... 12 + 580 ns + 400 ns (L2 TLB Miss)

Pipeline

Branch misprediction penalty = 6 cycles.

# Stage L/S Description
1 Fe1 Instruction fetch + dynamic branch prediction
2 Fe2
3 De Decode + static branch prediction + Return Stack
4 Iss Unstruction issue + Register read
5 Sh ADD Shifter / Address generation
6 ALU DC1 Main integer operation calculation / First stage of data cache access
7 Sat DC2 Saturation of integer results / Second stage of data cache access
8 WBex WBls Write back

Links

ARM11 at Wikipedia

The ARM11 Microarchitecture. David Cormie

ARM1136JF-S and ARM1136J-S. Technical Reference Manual