Intel Atom

Atom N2800

Atom N2800 (32 nm, Cedarview-M, CPU ID: 00030661 ) @ 1862 MHz (14.00 x 133.3 MHz). ASUS 1025C.

DDR3 533.3 MHz (PC3-8500), 7-7-7-20.

4 KB pages, 32-bit Windows (PAE)

  Size        Latency       Increase   Description

  24 K     3
  32 K     6               3           + 12 (L1 cache miss)
  64 K    11               5
 128 K    17               6           + 7 (L1 DTLB miss)
 256 K    20               3
 512 K    30              10           + 16 (L2 TLB miss) 
   1 M    34 +  50 ns      4 + 50 ns   + 85 ns (RAM)
   2 M    37 +  70 ns      3 + 20 ns
   4 M    40 +  80 ns      3 + 10 ns
   8 M    44 +  83 ns      4 +  3 ns   + 12 (Page walk to L2 cache) ?
  16 M    48 +  85 ns      4 +  2 ns
  32 M    50 +  90 ns      2 +  5 ns
  64 M    50 + 108 ns          18 ns
 128 M    50 + 133 ns          25 ns 
 256 M    50 + 155 ns          22 ns 
 512 M    50 + 170 ns          15 ns   + 85 ns (Page walk to RAM)

64-bytes range cross penalty = 14 cycles.

4 MB pages, 32-bit Linux

  Size        Latency        Increase   Description

  24 K     3
  32 K     6               3            + 12 (L1 cache miss)
  64 K    11               5
 128 K    17               6            + 7 (L1 DTLB miss)
 256 K    20               3
 512 K    22               2 
   1 M    22 +  50 ns          50 ns    + 85 ns (RAM)
   2 M    22 +  70 ns          20 ns
   4 M    22 +  80 ns          10 ns
   8 M    22 +  83 ns           3 ns
  16 M    22 +  85 ns           2 ns
  32 M    22 +  85 ns
  64 M    36 +  85 ns     14            + 28 (L2 TLB miss)
 128 M    43 +  85 ns      7
 256 M    47 +  85 ns      4
 512 M    49 +  85 ns      2
1024 M    50 +  85 ns      1

Atom N270

Atom N270 (45 nm, C0) @ 1600 MHz , FSB: 533 + i945GSE (rev. 03) + DDR2-533 (4-4-4-12-16) 1024 MBytes.

4 KB pages mode

L2 TLB size = 64 items. Miss penalty = 16

Size Latency Description
24 K 3 L1-TLB + L1
64 K 15 + 12 (L1-Cache miss)
256 K 22 + 7 (L1-TLB miss)
512 K 38 + 16 (L2-TLB miss)
... 38 + 115 ns + RAM

Pipeline

Branch misprediction penalty = 14 cycles.

Integer pipeline:

# Name Description
1 IF1 Instruction Fetch
2 IF2
3 IF3
4 ID1 Instruction Decode
5 ID2
6 ID3
7 SC Instruction Dispatch
8 IS
9 IRF Source Operand Read
10 AG Data Cache Access
11 DC1
12 DC2
13 EX1 Execute
14 FT1 Exceptions and MT handling
15 FT2
16 IWB/DC1 Commit

Links

Intel Atom at Wikipedia