Sony Cell

Configuration

Sony Cell. 256 MB (XDR DRAM 400MHz).

235M-250M Transistors, 235 mm2, 90 nm CMOS SOI, 8 metal layers, FC PBGA. Sony Cell.

Power Processor Element (PPE)

4 KB pages mode (Linux)

Size Latency Description
32 K 5 ERAT + L1
256 K 41 +36 (L2)
512 K 65 +24 (ERAT miss -> TLB hit)
4 MB 65 + 120 ns + 120 ns (RAM)
... 65 + 240 ns + 120 ns (TLB miss)

Pipeline

Branch misprediction penalty = 24 cycles.

Integer pipeline:

# Description Stage Stage2
1 Cache IC1
2 IC2
3 IC3
4 IC4
5 Buffer IB1 BP1
6 IB2 BP2
7 Decode ID1 BP3
8 ID2 BP4
9 ID3
10 Issue IS1
11 IS2
12 IS3
13 Delay . RF1
14 . RF2
15 . MEM1
16 Register RF1 MEM2
17 RF2 MEM3
18 Execute EX1 MEM4
19 EX2 MEM5
20 EX3 .
21 EX4 .
22 EX5 .
23 Writeback WB WB

Links

Cell at Wikipedia

Cell Broadband Engine resource center at IBM

Cell Broadband Engine downloads at Sony