ARM Cortex-A8

L1 Data cache = 32 KB. 4-Way, 64 B/line. HVAB: additional 6-bit TAG (hashed value produced from VA:13-31 and ASID/PID) for each cache line to speed up data cache way select in case of hit, so it doesn't need TLB and full tag read / compare in critical read path.
L1 Instruction cache = 32 KB.
L2 cache = 256-512 KB. 64 B/line.
Data TLB size = 32 items.
Instruction TLB size = 32 items.
In-order, dual-issue, superscalar microprocessor core
13-stage main integer pipeline
10-stage NEON media pipeline for executing NEON and VFP instruction sets
BTB (Branch Target Buffer): 512 entries
GHB (Global history Buffer): 4096 * 2bit (accessed via 10-bit Global branch history and 4 low bits of PC).
Return Stack: 8 entries. Fetch unit maintains both a speculative and non-speculative return stack. The speculative return stack is read and updated immediately based on the information returned from the BTB access while the non-speculative stack is not updated until the branch is known to be non-speculative at the end of the pipeline. If a branch is mispredicted, then the state of the speculative stack is overwritten by the state in the non-speculative stack.
2 * ALU, MUL, LS

Freescale i.MX515

Freescale i.MX515, 800 MHz.

L2 Read B/W (64 Bytes stride) = 13 cycles per 64-byte cache line
RAM Read B/W (4 Bytes stride) = 260 MB/s
RAM Read B/W (64 Bytes stride) = 290 MB/s
RAM Write B/W (any stride) = 220 MB/s (18 ns per 4-byte write). Write-Allocate for L2 was disabled

TI DM3730, 1000 MHz.

16-bytes range cross penalty = 9 cycles
L2 Read B/W (64 Bytes stride) = 11 cycles per 64-byte cache line
RAM Read B/W (4 Bytes stride) = 360 MB/s
RAM Read B/W (64 Bytes stride) = 400 MB/s
RAM Write B/W (4 Bytes stride) = 1500 MB/s, Write-Allocate probably was disabled

Samsung Hummingbird, 1000 MHz.

16-bytes range cross penalty = 9 cycles
L2 Read B/W (64 Bytes stride) = 13 cycles per 64-byte cache line
RAM Read B/W (4 Bytes stride) = 480 MB/s
RAM Read B/W (64 Bytes stride) = 570 MB/s
RAM Write B/W (4 Bytes stride) = 1500 MB/s, Write-Allocate probably was disabled

Branch misprediction penalty = 13-14 cycles.

Integer pipeline (from ARM's presentations):

#	Name	Stage	Description2
1	F0	Fetch	AGU
2	F1		RAM TLB BTB 512-entry 2-way GHB 4096 * 2 bit Return Stack: 8 entries
3	F2		12-entry Fetch Queue
4	D0	Decode	Early Dec
5	D1		Dec / Sec
6	D2		Dec Queue read / write
7	D3		Score-Board + Issue Logic
8	D4		RegFile + ID + remap
9	E0	Execute	Architectular RegFile
10	E1		MUL 1 / Shift / Shift / AGU
11	E2		MUL 2 / ALU+flags / ALU+flags / RAM + TLB
12	E3		MUL 3 / Sat / Sat / Format forward
13	E4 / L1		ACC / BP update / BP update / L2 Update - Arb
14	E5 / L2		WB / WB / WB / L2 tag : RAM 1
15	L3	L2 Load	L2 tag : RAM 2
16	L4		Tag miss
17	L5		L2 data : RAM 1
18	L6		L2 data : RAM 2
19	L7		L2 data : RAM 3
20	L8		Bank mux
21	L9		Data format