Intel Itanium 2

Configuration

1300 MHz (Madison, 130 nm) (HP rx2600, RAM: : PC2100 ECC Registered DDR266A).

Cache

16 KB pages mode

Size Latency Description
16 K 2 L1 TLB + L1
128 K 6 + 4 (L1 miss -> L2 hit)
256 K 10 + 4 (L1-TLB miss -> L2-TLB hit)
2M 20 + 10 (L2 miss -> L3 hit)
3M 35 + 15 (L2-TLB miss -> VHPT walker to L2-Cache)
... 35 + 160 ns + RAM (L3-Cache Miss)

Note: L1 latency is 1 Cycle, if data is used for ALU

Pipeline

# Name Description
1 IPG Instruction pointer generation. L1 ILTB, L1I, access.
2 ROT Instruction rotation.
3 EXP Instruction template decode, expand, and disperse.
4 REN Rename (for register stack and rotating registers) and decode.
5 REG Register file read.
6 EXE ALU execution
7 DET Last stage for exception detection.
8 WRB Write Back.

Links

Itanium 2 at Wikipedia

Itanium at Intel