AMD K5

Cache

AMD K5 75 (75 x 1), FIC VA-503 (Via VP3, L2 1MB, PC133 SDRAM).

4 KB pages mode

Size Latency Description
8 K 1 TLB + L1
512 K 10 + 9 (L1-Cache miss, L2 hit)
1 M 25 +15 (TLB miss)
... 25 + 100 ns + 100 ns (RAM)

AMD K5 75 MHz (50 MHz x 1.5) : Zida 5STX 1.02 (Intel 430TX, L2 512MB, RAM: 16MB - 2xSIMM 4xHY5118160 JC-70).

4 KB pages mode

Size Latency Description
8 K 1 TLB + L1
512 K 15 + 14 (L1-Cache miss, L2 hit)
... 32 + 270 ns +17 (TLB miss) + 270 ns (RAM)

Pipeline

Branch misprediction penalty = 3 cycles?

# Name Description
1 Fetch Calculate Fetch PC
Fetch instruction.
Predict branch
2 Decode1 Shift instructions to 16-byte FIFO byte queue.
Generate ROPs.
3 Decode2 Drive ROPs to decode.
Access registers or ROB.
4 Execute Dispatch to function unit. calculate address and dcache index
Execute.
Access Cache
5 Result Result on Bus.
Write ROB.
Branch correction
.
6 Retire Write to register.
ROB forwarding
.

Links

AMD K5 at Wikipedia

AMD's K5 Designed to Outrun Pentium, Michael Slater, Microprocessor Report.