MIPS 4K

TI AR7 (MIPS 4KEc) 150 MHz

4 KB pages mode

Size Latency Description
16 K 2 TLB + L1
128 K 2 + 240 ns + 240 ns (RAM)
... 2 + 460 ns + 220 ns (TLB miss)

Pipeline

# Name Description
1 Instruction I-TLB translation.
An instruction is fetched from the ICache.
An instruction is fetched from the ICache.
2 Execution Instruction decode.
Operands are fetched from the register file.
Instruction logic selects an instruction address.
ALU operation begins.
ALU calculates the data virtual address for load and store instructions.
ALU resolves branch conditions and calculates branch target address.
Instruction logic selects an instruction address.
3 Memory ALU operation completes.
Data TLB and data cache lookup.
The data cache fetch and VA->PA translation.
The data cache fetch and VA->PA translation.
4 Align / Accumulate A separate aligner aligns loaded data with its word boundary.
.
5 Writeback Result is written back to the register file.
.

Links

MIPS 4KE Family