MIPS 74K

Atheros AR9344 (MIPS 74K), 560MHz, 128 MB (16-bit DDR2-667D x 2). TP-Link WDR3600.

4 KB pages

  32 K     4                              TLB + L1
  64 K     4 +  80 ns           80 ns     + 150 ns RAM
 128 K     4 + 120 ns           40 ns
 256 K     4 + 140 ns           20 ns          
 512 K    24 + 200 ns      20 + 60 ns     + 40 + 100 ns (TLB miss)
   1 M    34 + 225 ns      10 + 25 ns
   2 M    39 + 237 ns       5 + 12 ns               
   4 M    42 + 246 ns       3 +  9 ns               
   8 M    44 + 260 ns       2 + 14 ns     
  16 M    44 + 290 ns           30 ns     + ??? ns (Page walk)
  32 M    44 + 340 ns           50 ns     
  64 M    44 + 370 ns           30 ns     

16 KB pages

  Size        Latency        Increase     Description

  32 K     4                              TLB + L1
  64 K     4 +  80 ns           80 ns     + 155 ns RAM
 128 K     4 + 120 ns           40 ns
 256 K     4 + 140 ns           20 ns          
 512 K     4 + 150 ns           10 ns
   1 M     4 + 155 ns            5 ns
   2 M    24 + 207 ns      20 + 52 ns     + 40 + 100 ns (TLB miss)               
   4 M    34 + 230 ns      10 + 23 ns               
   8 M    39 + 243 ns       5 + 13 ns     
  16 M    43 + 248 ns       3 +  5 ns     
  32 M    44 + 259 ns       2 + 11 ns     
  64 M    44 + 294 ns           35 ns     + ??? ns (Page walk)

Branch misprediction penalty = 10 cycles.

Cache aliasing problem (32 KB data cache, 4-way, 4 KB pages): There is some penalty for data cache accesses, if there are some uninitialized data in cache (the data from another process?).

MIPS 74K

Integer pipeline:

Unit # Stage Name Description
Fetch
(IFU)
1 IT Instruction Tag Read I-cache tag arrays accessed
Branch History Table, JRC accessed
ITLB address translation performed
Instruction watch and EJTAG break comparesdone
2 ID Instruction Data Read I-cache data array accesses
Tag compare, Detect I-cache hit
3 IS Instruction Select Way select
Target calculation start
4 IB Instruction Buffer Instruction Buffer write
Target calculation done
Decode &
Despatch
(IDU)
5 DD Decode Access Rename Map, get source register availability to resolve source dependency
Decode instructions and assign pipe and instruction identifier
Check execution resources
6 DR Rename Update Rename Map at destination register to resolve output dependency
Send instruction information to Graduation Unit (GRU)
Send instruction to Decode and Dispatch Queue (DDQ)
7 DS Select for Dispatch Check for operand and resource availability and mark valid instructions as ready for dispatch
Select 1 out of 8 (6-entry DDQ + 2 staging registers) ready instructions in each ALU and AGEN pipe independently
8 DM Instruction Mux Read out the selected instruction from the previous stage and update the selection information
Generate controls for source-operand bypass mux
ALU pipe will start premuxing operands based on the selected instruction
AGEN pipe will starting reading source operands from Register File and Completion Buffers.
ALU 9 AF ALU Register File Read
10 AM ALU Operand Mux
11 AC ALU Compute
12 AB ALU Results Bypass
Graduation
Unit
(GRU)
13 WB Writeback
14 WC Graduation Complete

Links

MIPS32 74K