VIA Nano U2250

Configuration

VIA Nano U2250 (65 nm) 1600 MHz (800 Mhz * 2)

Cache

L1 Data cache = 64 KB. 64 B/line, 16-WAY.

L1 Instruction cache = 64 KB.

L2 cache size = 1024 KB. 64 B/line, 16-WAY

4 KB pages mode

TLB size = 128 items. Miss penalty = 53

Size Latency Description
64 K 4 TLB + L1
512 K 24 +20 (L2)
1 M 77 +53 (TLB miss)
... 77 + 100 ns + RAM

MISC

32-bytes range cross penalty = 14 cycles.

4096-bytes range cross penalty = 33 cycles.

L2 Read B/W with 64 Bytes stride = 17 cycles per cache line

L2 Read B/W with Parallel Random Read = 13 cycles per cache line

L2 Write B/W with 64 Bytes stride = 12 cycles per cache line

RAM Read B/W with 4 Bytes stride = 1500 MB/s

RAM Read B/W with 64 Bytes stride = 3500 MB/s

RAM Write B/W with 4-64 Bytes stride = 1200 - 1400 MB/s

Branch misprediction penalty = 18 cycles.