HP J6000, 278-pin 120MHz ECC SDRAM DIMMs.
HP PA-8600, 250 nm, 5-layer metal CMOS, 21.3 * 22.0 mm2 die, 140,000,000 FETs,
5-layer metal CMOS packaged in a 544-pin LGA package.
- Data cache = 1024 KB. 4-Way, 64 B/line (32 B/line supported ?), round-robin replacement, 2-cycle pipelined access, 2 accesses per cycle,
- Instruction cache = = 512 KB. 4-Way, 32/64 B/line, Quasi LRU, 2-cycle access, 4 instructions per cycle.
- TLB: 160 entries, fully-associative, dual-ported
- 40-bit physical addresses
- Out of Order, 4-way superscalar
- 10 functional units: 2 integer ALUs, 2 shift/merge units, 2 complete load/store pipelines, 2 Floating Point multiply/accumulate units, 2 Floating Point divide/square root units
- 56-entry instruction queue/reorder buffer (IRB) : 28 (ALU/FP) + 28 (MEM).
- Execute: Up to two ALU/FP instructions and two MEM instructions each cycle.
- Retire: In Order, Up to two ALU/FP instructions and two MEM instructions each cycle.
- 32-entry BTAC (branch target address cache)
- 2048-entry BHT (branch history table).
- Dynamic and static branch prediction modes
- Bi-endian support
- Runway+/Runway DDR system/memory bus, 125MHz, 64-bit, DDR (double data rate), about 2.0GB/s peak bandwidth
CONS: PA-RISC doesn't support Multiply operation with integer registers.
So compiler can produce the sequence of instructions for just one integer Multiply:
the transfer operands from integer registers to float registers (via memory),
float register Multiply,
and the transfer of result from float register to integer register.
4 KB pages mode
|640 KB ||3 ||TLB + Cache |
|1 MB ||3 + 200 ns ||+ 200 ns (TLB miss) |
|... ||3 + 380 ns || + 180 ns (RAM access) |
- 4-bytes range cross penalty = 681 cycles.
- Parallel accesses is delayed, if TLB miss.
- RAM Read B/W (4 Bytes stride) = 490 MB/s
- RAM Read B/W (64 Bytes stride) = 1000 MB/s
- RAM Write B/W (4 Bytes stride) = 490 MB/s (write-allocate enabled via MSR)
- RAM Write B/W (64 Bytes stride) = 660 MB/s (write-allocate enabled via MSR)
|1 ||IF0 ||Instruction Fetch |
|2 ||IF1 |
|3 ||DEC ||Instruction Decode |
|4 ||QU ||Insert in I-Queue |
|5 ||ARB ||Arbitrate |
|6 ||EX / AC ||Execute / Address Calculate |
|7 ||WB / DC0 ||Write Result / Data Cache 0 |
|8 || / DC1 ||/ Data Cache |
|9 || / WB || / Write Result |
PA-RISC at Wikipedia
PA-8000 at Wikipedia
PA-RISC Processors at OpenPA.net