Cavium ThunderX

Cavium ThunderX, 2.0 GHz, (28 nm ?). 4 virtual cores.

L1 Data cache = 32 KB, 128 B/line, ?-WAY.
L1 Instruction cache = 78 KB, ? B/line, ?-WAY.
L2 Cache = 16 MB, 128 B/line, ?-WAY, shared by all cores.

L1 Data Cache Latency = 3 cycles for simple access via pointer
L1 Data Cache Latency = 3 cycles for access with complex address calculation (size_t n, *p; n = p[n]).
L2 Cache Latency = 42 cycles
RAM Latency = 42 cycles + 75 ns

2-wide issue?

512 MB pages THP in guest OS - 64-bit Ubuntu, unknown page size in host OS

Data TLB L1 (64 KB pages): 32 items. ?-way. Miss penalty = 17 cycles. Parallel miss: 18 cycles per access
Data TLB L2 (64 KB pages): 128 items. ?-way. Miss penalty = 70 cycles. Parallel miss: 130 cycles per access

64 KB pages (THP off) in guest OS - 64-bit Ubuntu, unknown page size in host OS

Data TLB L1: 32 items. ?-way. Miss penalty = 17 cycles. Parallel miss: 18 cycles per access
Data TLB L2: 128 items. ?-way. Miss penalty = 130 cycles. Parallel miss: 190 cycles per access

  Size        Latency       Increase   Description

  32 K     3                           
  64 K    23                      20   + 39 (L2)        
 128 K    33                      10   
 256 K    38                       5
 512 K    40                       2   
   1 M    41                       1
   2 M    42                       1
   4 M    51                       9   + 17 (L1 TLB miss)        
   8 M    56               5 +  
  16 M   125 + 13 ns      69 + 13 ns   + 130 (L2 TLB miss)
  32 M   157 + 43 ns      32 + 30 ns   + 75 ns (RAM)
  64 M   173 + 59 ns      16 + 16 ns
 128 M   181 + 67 ns       8 +  8 ns
 256 M   185 + 71 ns       4 +  4 ns
 512 M   187 + 73 ns       2 +  2 ns
   1 G   188 + 74 ns       1 +  1 ns
   2 G   189 + 75 ns       1 +  1 ns
   4 G   189 + 75 ns         
...

MISC

Branch misprediction penalty = 7-8 cycles

4-bytes range cross - ?
8-bytes range cross penalty = 9 cycles
Page cross - no additional penalty

L1 B/W (Parallel Random Read) = 1 cycle per one access

L2->L1 B/W (Parallel Random Read) = 42.00 cycles per cache line (no parallel access)
L2->L1 B/W (Read, 64 bytes step) = 42 cycles per cache line (no HW prefetch L2->L1)

RAM Read B/W (Parallel Random Read) = (190 cycles + 75 ns) / access line (no parallel access)
RAM Read B/W (Read, 8-64 Bytes step) = 1300 MB/s (no HW prefetch from RAM)
RAM Write B/W (Write, 8 Bytes step) = 10300 MB/s

7-Zip Benchmark

Linux-4.2.0 (virtSoC), gcc-6 -march=armv8-a -O2 -mcpu=thunderx

Note: MIPS and Effectiveness values are normalized with AMD K8 cpu.


7z b -mm=* -mmt1

7-Zip (a) [64] 15.09 beta : Copyright (c) 1999-2015 Igor Pavlov : 2015-10-16
p7zip Version 15.09 beta (locale=en_US.UTF-8,Utf16=on,HugeFiles=on,64 bits,4 CPUs LE)

LE
CPU Freq:  1954  1953  1956  1964  1966  1973  1971  1964  1963

RAM size:    8102 MB,  # CPU hardware threads:   4
RAM usage:    211 MB,  # Benchmark threads:      1


Method           Speed Usage    R/U Rating   E/U Effec
                 KiB/s     %   MIPS   MIPS     %     %

CPU                      100   1968   1968
CPU                      100   1966   1966
CPU                      100   1966   1966   100   100

LZMA:x1           4966   100   1816   1816    92    92
                 23240   100   1871   1871    95    95
LZMA:x5:mt1       1109   100   1386   1386    70    70
                 22385   100   1883   1883    96    96
LZMA:x5:mt2       2120   182   1458   2649    74   135
                 22262   100   1872   1872    95    95
Deflate:x1       10553   100   1340   1340    68    68
                 45972   100   1422   1422    72    72
Deflate:x5        4463   100   1719   1719    87    87
                 46210   100   1424   1424    72    72
Deflate:x7        1588   100   1760   1760    89    89
                 46224   100   1424   1424    72    72
Deflate64:x5      4159   100   1797   1797    91    91
                 45495   100   1413   1413    72    72
BZip2:x1          2099   100   1269   1269    65    65
                 11661   100   1248   1248    63    63
BZip2:x5          1833   100   1530   1530    78    78
                 10245   100   1991   1991   101   101
BZip2:x5:mt2      3535   195   1515   2950    77   150
                 16812   165   1984   3267   101   166
BZip2:x7           550   100   1426   1426    73    73
                 10115   100   1965   1964   100   100
PPMD:x1           1415   100   1464   1464    74    74
                  1023   100   1205   1205    61    61
PPMD:x5            864   100   1466   1466    75    75
                   666   100   1248   1248    63    63
Delta:4         204106   100   1254   1254    64    64
                169279   100   1040   1040    53    53
BCJ             384748   100   1576   1576    80    80
                384284   100   1574   1574    80    80
AES256CBC:1      53952   100   1326   1326    67    67
                 46108   100   1133   1133    58    58
AES256CBC:2 

CRC32:1         262729   100   1913   1913    97    97
CRC32:4         502719   100   1122   1122    57    57
CRC32:8         682298   100    925    925    47    47
CRC64           503343   100   1031   1031    52    52
SHA256           72064   100   1470   1470    75    75
SHA1             99592   100    932    932    47    47
BLAKE2sp         80910   100   1780   1780    91    91

CPU                      100   1968   1968
------------------------------------------------------
Tot:                     111   1587   1756    80    89