AMD Zen

AMD Ryzen 7 1700X (Zen), 3.9 GHz (XFR), 14 nm. RAM: 32 GB, RAM DDR4-2600 (PC4-20800, dual channel)

L1 Data Cache Latency:

CCX L3:

Ryzen 1xxx: L3 Cache Latency (random access):

Ryzen 2xxx: L3 Cache Latency (random access):

CCX L3 Latency penalty for reading from different L3 Slices to Cores:

                 +4c
Core-0  Slice-0 ====== Slice-2  Core-2
          ||            ||    
      +2c ||            || +2c
          ||            ||    
Core-1  Slice-1 ====== Slice-3  Core-3
                 +4c 

Note: These penalty numbers are total penalties that include data request and data response. The hop latency for one direction must be 2 times lower.

Infinity Fabric

Infinity fabric links in Threadripper and Epyc for path from CCX to Memory Controller:

Local Memory access: CCX - xC - xM - MemCtl

Remote Memory access with 1 hop: CCX - xC - x6 - x3 - CAKE --- CAKE - x3 - x6 - xP - xM - MemCtl

Remote Memory access with 2 hops (short): CCX - xC - x6 - x3 - CAKE --- CAKE - x3 - CAKE --- CAKE - x3 - x6 - xP - xM - MemCtl

Remote Memory access with 2 hops (long): CCX - xC - x6 - x3 - CAKE --- CAKE - x3 - x6 - x3 - CAKE --- CAKE - x3 - x6 - xP - xM - MemCtl

Estimated latencies in Infinity Fabric clock cycles (1200/1333/1467/1600 MHz):

1 GB pages (64-bit)

  Size        Latency       Increase   Description

  32 K     4                           
  64 K    11                       7   + 13 (L2)        
 128 K    14                       3   
 256 K    16                       2
 512 K    17                       1   
   1 M    29                      12   + 23 (L3)
   2 M    35                       6
   4 M    37                       2
   8 M    39 +  5 ns       2 +  5 ns
  16 M    40 + 48 ns       1 + 43 ns   + 90 ns (RAM)
  32 M    40 + 70 ns           22 ns
  64 M    40 + 81 ns           11 ns
 128 M    40 + 86 ns            5 ns   
 256 M    40 + 88 ns            2 ns
 512 M    40 + 89 ns            1 ns
1024 M    40 + 90 ns            1 ns

2 MB pages (32-bit)

  Size        Latency       Increase   Description

  32 K     4                           
  64 K    11                       7   + 13 (L2)        
 128 K    14                       3   
 256 K    16                       2
 512 K    17                       1   
   1 M    29                      12   + 23 (L3)
   2 M    35                       6
   4 M    37                       2
   8 M    39 +  5 ns       2 +  5 ns
  16 M    40 + 48 ns       1 + 43 ns   + 90 ns (RAM)
  32 M    40 + 70 ns           22 ns
  64 M    40 + 81 ns           11 ns
 128 M    40 + 86 ns            5 ns   
 256 M    44 + 88 ns       4 +  2 ns   + 8 (L1 TLB miss)
 512 M    46 + 89 ns       2 +  1 ns   
1024 M    47 + 90 ns       1 +  1 ns   

4 KB pages mode (64-bit)

  Size        Latency       Increase   Description

  32 K     4                           
  64 K    11                       7   + 13 (L2)        
 128 K    14                       3   
 256 K    16                       2
 512 K    20                       4   + 8 (L1 TLB miss)
   1 M    35                      15   + 23 (L3)
   2 M    42                       7
   4 M    45                       3	
   8 M    63 +  5 ns      18 +  5 ns   + 34 ? (L2 TLB miss)
  16 M    72 + 48 ns       9 + 43 ns   + 90 ns (RAM)
  32 M    82 + 70 ns      10 + 22 ns
  64 M    87 + 81 ns       5 + 11 ns
 128 M    97 + 86 ns      10 +  5 ns   
 256 M   109 + 88 ns      10 +  2 ns
 512 M   113 + 89 ns       4 +  1 ns
1024 M   125 + 90 ns      12 +  1 ns

MISC

Links

Zen at Wikipedia

Zen at Wikichip