AMD Zen2

AMD 3800X (Zen2), 7 nm. RAM: 32 GB, RAM DDR4-3200 16-18-18-38-56-1T (dual channel)

L1 Data Cache Latency:

Note: Zen2 in Windows 10 probably can use Page Table Entry (PTE) Coalescing. The benchmark results show that TLB misses start for blocks that are 4 times larger than expected for 4 KB pages. So each item in L1 DTLB and L2 TLB probably cover 16 KB data (4 Coalesced 4 KB pages). We don't know how it's implemented: does OS software (Windows/Linux) need special support for it?

1 GB pages (64-bit)

  Size        Latency       Increase   Description

  32 K     4                           
  64 K     8                       4   + 8 (L2)        
 128 K    10                       2   
 256 K    11                       1
 512 K    12                       1   
   1 M    25                      13   + 26 (L3)
   2 M    32                       7
   4 M    35                       3
   8 M    37                       2
  16 M    38 +  4 ns        1 + 4 ns   
  32 M    38 + 40 ns           36 ns   + 66 ns (RAM)
  64 M    38 + 55 ns           15 ns
 128 M    38 + 62 ns            7 ns   
 256 M    38 + 63 ns            2 ns
 512 M    38 + 65 ns            1 ns
1024 M    38 + 66 ns            1 ns

2 MB pages (32-bit)

  Size        Latency       Increase   Description

  32 K     4                           
  64 K     8                       4   + 8 (L2)        
 128 K    10                       2   
 256 K    11                       1
 512 K    12                       1   
   1 M    25                      13   + 26 (L3)
   2 M    32                       7
   4 M    35                       3
   8 M    37                       2
  16 M    38 +  4 ns        1 + 4 ns   
  32 M    38 + 41 ns           37 ns   + 66 ns (RAM)
  64 M    38 + 55 ns           16 ns
 128 M    38 + 62 ns            7 ns   
 256 M    42 + 63 ns        4+  2 ns   + 7 (L1 TLB miss)
 512 M    44 + 65 ns        2+  1 ns
1024 M    45 + 66 ns        1+  1 ns

4 KB pages mode (64-bit)

  Size        Latency       Increase   Description

  32 K     4                           
  64 K     8                       4   + 8 (L2)        
 128 K    10                       2   
 256 K    11                       1
 512 K    12                       1   
   1 M    26                      14   + 26 (L3) 
   2 M    37                      11   + 7 (L1 TLB miss)
   4 M    41                       4	
   8 M    43                       2    
  16 M    44 +  6 ns       1 +  6 ns   
  32 M    45 + 41 ns       1 + 35 ns   + 66 ns (RAM)
  64 M    73 + 55 ns      28 + 21 ns   + 56 (L2 TLB miss)

MISC

Links

Zen 2 at Wikipedia

Zen 2 at WikiChip